2 byte compare

module compare_2_byte(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;output A_lt_B,A_gt_B,A_eq_B;wire w1,w2,w3,w4,w5,w6,w7;or(A_lt_B,w1,w2,w3);nor(A_gt_B,A_lt_B,A_eq_B);and(A_eq_B,w4,w5);and(w1,w6,B1);and(w2,w6,w7,B0);and(w3,w7,B0,B1);not(w6,A1);not(w7,A0);xnor(w4,A1,B1);xnor(w5,A0,B0);
endmodule-------------------------------------------------------------module compare_2a(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;output A_lt_B,A_gt_B,A_eq_B;asign A-lt_B=(~A1)&B1(-A1)&(~A0)&B0(~A0)&B1&B0;asign A_gt_B=A1&(-B1)A0&(~B1)&(~B0)A1&A0&(~B0);


method 3

asign A_lt_B=({a1,a0}<{b1,b0});
return 1 if ture else 0

method 4
always@(A or B)
if(A==B)A_eq_B=1;

1 byte compare

Fadd complete

module top;
wire a,b,sum,c_out,c_in;
system_clock #25 clock1(a);
system_clock #50 clock1(b);
system_clock #100 clock1(c_in);
add_full acz(sum,c_out,a,b,c_in);endmodule

module add_half_1(sum,c_out,a,b);
input a,b;output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module add_full(sum,c_out,a,b,c_in);
input a,b,c_in;output c_out,sum;
wire w1,w2,w3;
add_half_1 M1(w1,w2,a,b);
add_half_1 M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

Full Adder

module fadd(sum,c_out,a,b,c_in);

input a,b,c_in;

output sum,c_out;

wire w1,w2,w3;

hadd M1(w1,w2,a,b);

hadd M2(sum,w3,w1,c_in);

or(c_out,w2,w3);

endmodule

SynaptiCAD 試用版

http://www.dyu.edu.tw/~cschen/Verilog%20Computer%20Design/SynaptiCAD.exe

HW2 half adder

module hadd(sum,c,a,b);
input a,b;
output c,sum;
wire c_bar;
xor(sum,a,b);
nand(c_bar,a,b);
not(c,c_bar);
endmodule

HW1

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);s
ystem_clock #50 clock2(b);
always#1 c=a&b;
endmodule

module system_clock(clk);
parameter p=100;
output clk;
reg clk;
initial
clk=0;
alwaysbegin#(p/2) clk=~clk;
#(p/2) clk=~clk;
end
always@(posedge clk)if($time>1000)#(p-1)$stop;
endmodule